| Autor: |
Verma, Km Anjali, Kumar, Manish, Kumar, Saurabh, Chauhan, R. K. |
| Předmět: |
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| Zdroj: |
International Journal of Electronics; 2023, Vol. 110 Issue 11, p2117-2135, 19p |
| Abstrakt: |
Calculating power and delay in VLSI circuits are two main challenges in designing CMOS VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor domino logic for power and delay reduction. The lector technique uses two leakage-controlled transistors, PMOS and NMOS. The gate terminal of PMOS is connected to the source of NMOS, and the gate terminal of NMOS is connected to the source of PMOS. NMOS transistor N5 is used in the proposed circuit, driven by a dynamic node, which helps to reduce the power. This manuscript uses the proposed technique to design a buffer, two-input – AND gate, OR gate, and XOR gate circuits. The logic gates are simulated on the gpdk 45 nm cadence virtuoso software tool. The simulation result shows that the proposed domino logic circuit significantly reduces power, delay, energy, and leakage current. Monte Carlo analysis is performed to study the mean and standard deviation of the proposed circuit with 1000 samples. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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