| Autor: |
Dinesh, S., Ramesh, S. M. |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2023, Vol. 2764 Issue 1, p1-6, 6p |
| Abstrakt: |
Area, power, and delay are the three important parameters of interest when designing any digital system. Often altering one of the parameters always results in the modification of other two parameters in a negative way. Say if area is to be reduced then either the power increases or the delay increases. Optimization happens when the extent of this modification is less when compared to the improvisation of our parameter of interest. As, adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents a similar approach in improvising theperformance of the carry select adder where the number of gates is reduced at a little cost of increasing the delay. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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