| Autor: |
Mishra, Alok Kumar, Anand, Shail, Singh, Nishant, Dhandapani, Vaithiyanathan, Kaur, Baljit |
| Zdroj: |
International Journal of Systems Assurance Engineering & Management; Oct2023, Vol. 14 Issue 5, p1726-1737, 12p |
| Abstrakt: |
In this paper, a high-performance priority encoder of the 2-dimensional array is investigated and modified. This work involves 64-bit priority encoder design and verification using Verilog and cadence virtuoso. For the Verilog code, Vivado has been used for the Artix-7 FPGA board. For Cadence virtuoso, GPDK 180 nm CMOS technology has been used. By using a reduced 2-D priority encoder, 1000 transistors have been saved. Due to this, the delay of the whole 64-bit priority encoder is reduced by 62.17% as compared to PE64 and 61.68% as compared to modified PE64. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
Full text from SpringerLink