| Autor: |
Chiang, Patrick, Daily, William J., Lee, Ming-Ju Edward, RameshSenthinathan, Yangjin Oh, Horowitz, Mark A. |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Apr2005, Vol. 40 Issue 4, p1004-1011, 8p, 6 Color Photographs, 14 Diagrams |
| Abstrakt: |
A 20-Gb/s transmitter is i implemented in 0.13-µm CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 220 -1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 µm × 350 µm, and 2.37 ps/15 ps, respectively. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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