| Autor: |
Miura, Noriyuki, Mizoguchi, Daisuke, Sakurai, Takayasu, Kuroda, Tadahiro |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Apr2005, Vol. 40 Issue 4, p829-837, 9p, 5 Black and White Photographs, 10 Diagrams, 4 Charts, 17 Graphs |
| Abstrakt: |
A wireless bus for stacked chips was development by utilizing inductive coupling among then inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive are designed for inductive nonreturn-to-zero where no signal is transmitted when data remains the same. At test chip was fabricated in 0.35-μm CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 42 and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 μm in 90-nm device generation,power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm2. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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