| Autor: |
Sarpeshkar, Rahul, Salthouse, Christopher, Sit, Ji-Jon, Baker, Michael W., Zhak, Serhii M., Lu, Timothy K. T., Lorenzo Turicchia, Stephanie Nalster |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Biomedical Engineering; Apr2005, Vol. 52 Issue 4, p711-727, 17p |
| Abstrakt: |
We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-pm BiCMOS technology ci with a power consumption of 211 pW and 77-dB dynamic range of operation. The 9.58 mm x 9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (AID)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear- implant systems of the future which require decades of operation n on a 100-mAli rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 pW power consumption of a JFET-but Tered electret mi- P crop hone and an associated on-chip microphone front end. An U automatic gain control circuit compresses the 77-dB input dy- a namic range into a narrower internal dynamic range (IDR) of u. 57 dB at which each of the 16 spectral channels of the processor ei operate. The output bits of the processor are scanned and reported Ii off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits U ensure robust operation of the processor in the high-RF-noise `S" environment typical of cochlear implant systems. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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