| Autor: |
Koob, John C., Leder, Daniel A., Sung, Raymond J., Brandon, Tyler L., Elliott, Duncan G., Cockburn, Bruce F., McIlrath, Lisa |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Mar2005, Vol. 13 Issue 3, p358-369, 12p, 14 Diagrams, 2 Charts, 3 Maps |
| Abstrakt: |
We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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