| Autor: |
Mamidala, Vijay Karthik, Qureshi, Vaseem Ahmed |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2023, Vol. 2477 Issue 1, p1-12, 12p |
| Abstrakt: |
For an adaptive FIR filter, a new approximation DA architecture is suggested. The weights of the filter are updated using the LMS algorithm. To increase the area and power efficiency of the filter, we merged the CSD number with the DA approach in this architecture. The DA computation is done without the use of a LUT. Instead, DA computation is done using registers. The partial products are added using the Wallace tree adder, which increases the filter's speed while reducing its complexity. The structure's device utilization data shows that the area and power efficiency are both better than earlier designs. The proposed structure is generated in Verilog and implemented in a Virtex FPGA device. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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