| Autor: |
Kumar, C. H. Ashok, Shashank, B., Venkatesh, K., Rajesh, M., Sailesh, P. |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2023, Vol. 2492 Issue 1, p1-6, 6p |
| Abstrakt: |
In the present days the electronic gadgets which are portable like mobiles etc which always used in the major part of our life. So now each and every electronic system or gadget mostly using the arithmetic circuits. So the adder which becomes the important part of the arithmetic circuit like multipliers. In the case of the high performing microprocessors it will almost consumes the thirty three percentage of the total power supplied. Therefore, we are improving the performance of the adders. Then the hybrid logic is mostly used for implementing the full adder circuits. So this hybrid logic style will helps us for better performance of the adders and also improves the delay performance. So by this technology it is giving the full swing outputs. This proposed circuit is simulated using Tanner EDA environment. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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