| Autor: |
Li, Jiping, Wang, Shuo, Zhao, Tianting, Yang, Xin, Xiao, Zhiming, Zhao, Yue |
| Předmět: |
|
| Zdroj: |
IEEJ Transactions on Electrical & Electronic Engineering; May2023, Vol. 18 Issue 6, p910-916, 7p |
| Abstrakt: |
This paper presents a novel frequency compensation scheme for the stability of low dropout regulator (LDO). The proposed compensation scheme introduces a zero in the voltage regulation loop to enlarge gain and phase margin at high‐frequencies. As a result, high open‐loop‐gain and improved load regulation performances are achieved, and a particular resistor is introduced in the compensation structure to cancel the voltage drop originating from cable resistances at the output to further improve the load regulation performance. The proposed LDO with wide input/output range and high‐power supply rejection is designed and implemented in a 180 nm CMOS process. The LDO operates with an input voltage range of 4–16 V, an output voltage range of 1.5–5 V and an output current range of 0–1000 mA. High open loop gain and high bandwidth are achieved, and the simulated performances of load regulation and line regulation are less than 32 μV/mA and less than 3 mV/V over the whole operation range, respectively. The on‐chip compensation capacitor required by the compensation module is only 1.8 pF. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
Plný text