| Abstrakt: |
This brief investigates the characteristics and impact of the metastabity of true single-phase clock DFFs used for catch detection in Vernier TDCs, and proposes a metastability error correction technique that automatically eliminates the metastability-induced errors of Vernier TDCs. The effectiveness of the proposed technique is assessed using an 8-stage Vernier TDC with metastability error correction catch-detect DFFs. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate the proposed technique completely eliminates metastability-induced errors of Vernier TDCs at the cost of an additional power, area, and delay. [ABSTRACT FROM AUTHOR] |
