| Autor: |
M. Khanghah, Meysam, Sadeghipour, Khosrov D., Kelly, Denis, Antony, Cleitus, Ossieur, Peter, Townsend, Paul D. |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Oct2022, Vol. 69 Issue 10, p3976-3988, 13p |
| Abstrakt: |
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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