| Autor: |
Singh, Pratik Kumar, Raj, Rohit, Kumar, Vivek, Pandey, Monalisa, Prasad, Santashraya, Islam, Aminul |
| Předmět: |
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| Zdroj: |
Microsystem Technologies; Dec2022, Vol. 28 Issue 12, p2807-2820, 14p |
| Abstrakt: |
This paper explores design of various components that are extensively used in digital circuits namely AND gate, OR gate, NAND gate, NOR gate and Full Adder using GDI Logic. Area and power dissipation of the circuits are one of the main issues encountered while fabrication of a chip. The design of AND gate, OR gate, NAND gate, NOR gate and Full Adder, which aims to solve these problems has been proposed in this paper. All the simulations are performed in SPICE using 32-nm CNTFET and results are tabulated showing comparison of circuit performance between Static, Domino, GDI and Transmission Gate (TG) Logic. The proposed GDI cell required 64% less transistors to implement the 1-bit Full Adder as compared with STATIC logic. AND gate realized with GDI logic consumes 6.26 × 10 4 times (6.04× 10 4 times) (8.92 × 10 4 times) lower average power than that of AND gate realized with STATIC logic (Domino logic) (TG logic). GDI AND gate also shows 2.89 × 10 4 times (1.51 × 10 4 times) (1.175 × 10 6 times) lower PDP than that of STATIC AND gate (Domino AND gate) (TG logic). The GDI OR exhibits 4.8 × 10 3 times (725 times) (528 times) lower PDP than that of STATIC OR (Domino OR) (TG OR). GDI 1-BIT Full Adder also shows 179 times (107 times) (787 times) lower PDP than that of STATIC 1-BIT Full Adder (Domino 1-BIT Full Adder) (TG based 1-BIT Full Adder). The NAND GDI logic showed 3.8 times less PDP as compared to TG logic style. Similarly, in case of NOR gate the PDP of the GDI realized circuit was 2 times lesser than PDP of TG based NOR gate. The comparison to establish the superiority of CNTFET based circuit over MOSFET realized circuit was also performed. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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