| Autor: |
Ananda, Geethashree, Shrinivasa, Praveena K., Mahadevappa, Suchitra, Kalegowda, Bhargavi, Patil, Chandrashekar M., Mallappa, Rudrappa K. |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2022, Vol. 2494 Issue 1, p1-10, 10p |
| Abstrakt: |
The Advanced Encryption Standard (AES) algorithm is a symmetric encryption algorithm which is much faster, secure and consumes less power when compared to the previous cryptographic algorithms like DES and RSA. It can be implemented in software as well as hardware. The paper compares the advantages and disadvantages of various implementation of AES algorithm and proposes the design of standard cells and macro cells for Application-Specific Integrated Circuit (ASIC) of AES. A total of 212 standard cells and 20405 instances were designed and implemented using cadence virtuoso. The cells were fully custom designed using 45 nm technology with minimum channel length of 50 nm. The total number of cells in proposed implementation was lesser than other ASIC implementations. There was a significant percentage of decrease in area, power and timing constraints when compared to GPDK045_SC. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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