| Autor: |
M, Pavan Kalyan Kumar, Jammu, Bhaskara Rao, Veeramachaneni, Sreehari, Mahammad Sk, Noor |
| Předmět: |
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| Zdroj: |
International Journal of Electronics Letters; Sep2022, Vol. 10 Issue 3, p272-282, 11p |
| Abstrakt: |
Decimal converter plays an essential role in decimal arithmetic operations. A decimal converter is used to convert binary partial products to Binary Coded Decimal. Here, the use of the converter cell decreases the delay of operation. In contrast to the previous shift + add3 implementations, the proposed cell is much more efficiently optimised due to which the speed of the overall conversion process is increased. The proposed cell shows an improvement in the delay of 9.33 % and a power-delay product of 11.96 % when compared to the previously proposed work. So, the proposed work can be a better substitute where faster conversions are required. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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