| Autor: |
Morishita, Fukashi, Hayashi, Isamu, Matsuoka, Hideto, Takahashi, Kazuhiro, Shigeta, Kuniyasu, Gyohten, Takayuki, Niiro, Mitsutaka, Noda, Hideyuki, Okamoto, Mako, Hachisuka, Atsushi, Amo, Atsushi, Shinkawata, Hiroki, Kasaoka, Tatsuo, Dosaka, Katsumi, Arimoto, Kazutami, Fujishima, Kazuyasu, Anami, Kenji, Yoshihara, Tsutomu |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jan2005, Vol. 40 Issue 1, p204-212, 9p, 19 Black and White Photographs, 12 Diagrams, 1 Chart, 9 Graphs |
| Abstrakt: |
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a powerdown data retention (PDDR) mode is developed. A 13.98-mm² 16-Mb embedded DRAM macro is fabricated in 0.13 µm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-µW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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