| Autor: |
Abderehman, Mohammed, Patidar, Jayprakash, Oza, Jay, Nigam, Yom, Khader, TM Abdul, Karfa, Chandan |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; May2022, Vol. 41 Issue 5, p1371-1385, 15p |
| Abstrakt: |
High-level synthesis (HLS) is a well-established framework used to translate high-level algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major prevailing bottleneck of HLS is the large gap between the design and verification processes. Presently, register transfer level (RTL) simulation is the primary platform used for HLS design verification. Although most of the state-of-the-art RTL simulators provide an abstracted user-friendly platform for verification, they are undesirably slow and sometimes incomprehensible to non-field-programmable gate array experts to debug. The alternative software simulators (C simulation) introduced by commercial HLS tools render faster simulation, but are not cycle accurate and are not capable to estimate design performance. In this article, we introduce an automatic cycle-accurate simulation tool, FastSim, that manipulates certain unique features of HLS design to extract a concise, well-indented, and debug-friendly C behavior from the synthesized RTL. Our simulation tool ensures RTL correctness, provides cycle accuracy, accurate performance estimation, and renders on an average around 300 times faster simulation compared to RTL simulators and comparable performance to that of software C simulators. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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