| Autor: |
Gaidioz, David, Cathelin, Andreia, Deval, Yann |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Microwave Theory & Techniques; Apr2022, Vol. 70 Issue 4, p2207-2216, 10p |
| Abstrakt: |
This article presents a 2.4-GHz low-power compact integer- $N$ ring oscillator-based phase-locked loop (PLL) for Internet of Things (IoT) applications. The proposed integer- $N$ PLL is based on a dual loop Offset-PLL topology to achieve a fine frequency resolution similar to conventional fractional- $N$ PLL. Not using a delta-sigma modulator (DSM) allows an expanded PLL bandwidth without deteriorating the overall noise performance. Implemented in 28 nm CMOS fully depleted silicon on insulator (FD-SOI) technology, the proposed architecture requires a 22-MHz internal reference frequency while achieving a 2-MHz frequency resolution and a 3-MHz PLL bandwidth. Measured prototypes perform −43.9 dBc reference spur, as an average value over all the bluetooth low energy (BLE) band and numerous tested dies, a jitter Figure-of-Merit of −229.6 dB for a power consumption of 0.87 mW and a core area of 0.0256 mm2. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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