| Autor: |
Panetas-Felouris, Orfeas, Vlassis, Spyridon |
| Předmět: |
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| Zdroj: |
Journal of Low Power Electronics & Applications; Mar2022, Vol. 12 Issue 1, p3-N.PAG, 11p |
| Abstrakt: |
This paper presents a novel circuit of a z−1 operation which is suitable, as a basic building block, for time-domain topologies and signal processing. The proposed circuit employs a time register circuit which is based on the capacitor discharging method. The large variation of the capacitor discharging slope over technology process and chip temperature variations which affect the z−1 accuracy is improved using a novel digital calibration loop. The circuit is designed using a 28 nm Samsung FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis presenting a variation of capacitor voltage discharging slope less than 5% over worst-case process corners for temperature between 0 °C and 100 °C while consuming only 30 μA. Also, the worst-case accuracy of z−1 operation is better than 33 ps for input pulse widths between 5 ns and 45 ns presenting huge improvement compared with the uncalibrated operator. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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