| Autor: |
Bhatia, Inderdeep Singh, Randhawa, Deep Kamal Kaur |
| Zdroj: |
SILICON (1876990X); Apr2022, Vol. 14 Issue 5, p2127-2134, 8p |
| Abstrakt: |
Almost 50% of random logic power is consumed in System-on-chip (SOC) by the memory latch circuits. VLSI designers of high performance SOC are struggling to realise a performance rich and energy efficient design method. A number of power optimisation techniques and methods have been suggested which ultimately increase hardware complexity. Consequently, due to more number of components the cost as well as the area used on chip increases. In this study the design and demonstration of D latch and S-R latch based on the Silicene based multiplexer device (SMLD) using Verilog-A is done. The working of SMLD based latches is validated through circuits simulations in SPICE. The SMLD based D latch and S-R latch show an improvement in hardware reduction by 93.75% and 50% respectively as compared to CMOS based D latch and S-R latch. Also the improvement in area utilization on chip by 94.10% and 52.83% is achieved by SMLD based D latch and S-R latch respectively. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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