| Abstrakt: |
A new architecture for the synthesis of fault-tolerant digital devices, which is easier to implement as compared to the well-known architecture based on triple modular redundancy (TMR), is proposed. The architecture is implemented based on the Boolean complement principle, which implies the use of a special control block for evaluating complement functions, rather than by introducing exact copies of an original circuit. In practice, its complexity can be significantly lower than the complexity of the original circuit. This makes it possible to synthesize fault-tolerant devices with simpler designs as compared to TMR-based devices. The proposed architecture consists of three blocks: the original circuit, the signal error detection circuit, and the signal correction circuit. The synthesis of a fault-tolerant digital device is aimed at generating the structure of the signal error detection circuit, which implements the idea of duplication of complements. The advantages and disadvantages of the proposed fault-tolerant architecture are discussed. The results of experiments on some combinational benchmarks, which demonstrate the effectiveness of the proposed approach, are presented. [ABSTRACT FROM AUTHOR] |
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