A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel kT / C -Canceling S&H and ΔΣADC.

Autor: Okada, Chihiro, Zeituni, Golan, Uemura, Koushi, Hung, Luong, Matsuura, Kouji, Moue, Takashi, Kodama, Kazutoshi, Okano, Masafumi, Morikawa, Takafumi, Yamashita, Kazuyoshi, Oka, Osamu, Inada, Yoshiaki, Shvartz, Itai, Shem, Ariel Ben, Eshel, Noam
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Zdroj: IEEE Journal of Solid-State Circuits; Nov2021, Vol. 56 Issue 11, p3228-3235, 8p
Abstrakt: This article presents a 50.1-Mpixel 14-bit 250-frames/s back-illuminated stacked CMOS image sensor on 35-mm optical format exhibiting 1.18- $\text{e}^{-}$ rms random noise at 0 dB. This sensor employs a load reduction technique by splitting half of pixel signal line using a Cu-Cu connection technology underneath the pixel area, pipelined operation with a gain-adaptive column-parallel kT/ $C$ noise-canceling sample and hold, and a 250-frames/s scanning rate and 14-bit resolution delta-sigma analog-to-digital converter (ADC) circuit. Moreover, an on-chip online calibration of column mismatch maintains the non-linearity of the output image within −0.42%. As a result, FoM6 ($\text{e}^\ast $ pJ/step) of 0.09 is obtained as the state-of-the-art performance. [ABSTRACT FROM AUTHOR]
Databáze: Complementary Index