| Autor: |
Pu, Junran, Goh, Wang Ling, Nambiar, Vishnu P., Chong, Yi Sheng, Do, Anh Tuan |
| Zdroj: |
IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Apr2021, Vol. 68 Issue 4, p1398-1402, 5p |
| Abstrakt: |
With the ability to generate different spiking patterns, Izhikevich model has well been considered a computationally efficient and biologically plausible neuron model for applications such as brain dynamic behavior study. This brief presents a low-cost, high-throughput digital hardware design for Izhikevich neuron model. The proposed design requires only addition, subtraction and logic shifts operations to achieve the low hardware cost. The dynamic behaviors of both the proposed neuron model and the original Izhikevich model were analyzed using the phase portraits. The FPGA implementation results demonstrated that the proposed design can reproduce different spiking patterns with very high throughput. Compared to existing designs, the proposed design achieves the lowest slices and LUTs utilization, which are 73% and 11% lower than the latest design (HOMIN), respectively. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
