| Abstrakt: |
Bilateral filter (BF) is a type of edge-preserving smoother that is widely utilized in most image processing, computational photography, and computer vision applications. This article presents FPGA implementation of a modified recursive box filter (MRBF)-based fast BF (FBF) architecture for reducing computational complexity, area, and power. In addition, implementation of MRBF uses a modified carry select adder using quantum-dot cellular automata technology that offers lower area, less power consumption, and less delay. Furthermore, as an application, an investigation of image denoising with the proposed MRBF-FBF is also performed. Extensive simulation and hardware results disclose that the proposed FPGA implementation of MRBF-FBF outperforms the conventional filtering techniques in terms of quality assessment of the denoised image, such as peak signal-to-noise ratio and structural similarity index. [ABSTRACT FROM AUTHOR] |
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