| Autor: |
Chae, J.‐H., Kim, M., Ko, H., Jeong, Y., Park, J., Hong, G.‐M., Jeong, D.‐K., Kim, S. |
| Zdroj: |
Electronics Letters (Wiley-Blackwell); Jun2017, Vol. 53 Issue 12, p766-768, 3p |
| Abstrakt: |
A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated phase interpolator (PI) to improve the jitter and linearity. The DLL consists of two kinds of DLLs: a global DLL to assist fast locking; and a local DLL which uses an adaptive‐window phase detector and a folded delay line to reduce jitter and improve linearity. The PI uses a triangular‐modulated clock waveform to achieve good linearity over a wide frequency range. The prototype chip is implemented in a 65 nm CMOS process. The measured jitter of the DLL is 3.08 psrms/19.93 pspp at 2133 MHz. The measured differential non‐linearity of the phase shifter is <0.91 LSB at 2133 MHz, and the power efficiency is about 2.7 mW/GHz. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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