| Autor: |
Sands, Kenneth D., Broadmeadow, Mark A. H., Walker, Geoffrey R. |
| Předmět: |
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| Zdroj: |
Journal of Engineering; Sep2019, Vol. 2019 Issue 9, p4122-4126, 5p |
| Abstrakt: |
This research presents a novel technique to synchronise a modular control and data acquisition system for the testing of multi-level power hardware-in-the-loop (PHIL) amplifiers. The methodology is inspired by the precision timing protocol, used to compensate for communications latency between distributed control nodes. It uses a non-conventional digital pulse-width modulation (PWM) technique, phase accumulator carrier pulse-width modulation to achieve carrier synchronisation across the system. A prototype design has been demonstrated on a three-node test bench, showing single clock cycle (10 ns) precision when synchronising a 25 kHz PWM carrier wave, with minimal sensitivity to communications link propagation delays. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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