Design of Ultrahigh-Speed Low-Voltage CMOS CML Buffers and Latches.

Autor: Heydari, Payam, Mohanavelu, Ravindran
Předmět:
Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2004, Vol. 12 Issue 10, p1081-1093, 13p, 9 Graphs
Abstrakt: In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time T (i.e., for T 0 and T → ∞). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-and- paper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes. [ABSTRACT FROM AUTHOR]
Databáze: Complementary Index