| Autor: |
Pirogov, A. A., Glotov, V. V., Pirogova, Yu. A., Gvozdenko, S. A., Bashkirov, A. V., Volkovich, Vladimir A, Kashin, Ilya V, Smirnov, Andrey A, Narkhov, Evgeniy D |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2020, Vol. 2316 Issue 1, p1-6, 6p |
| Abstrakt: |
FPGA are configurable integrated circuits, the logic of which is determined by programming them. The use of FPGA for the tasks of digital signal processing allows you to get devices that can change configuration, adapt to a specific task due to their flexible, programmable structure. When developing complex devices, ready-made blocks – IP- cores (intellectual property cores) can be used as components for design. The use of software IP-cores allows you to most effectively use them in the final structure, to significantly reduce the cost of design. The purpose of the work is to build an RTL model of the IP-core of digital signal processing, its verification at both the logical and physical level. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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