| Autor: |
Farjad-Rad, Ramin, Nguyen, Anhtuyet, Tran, James M., Greer, Trey, Poulton, John, Dally, William J., Edmondson, John H., Senthinathan, Ramesh, Rathi, Rohit, Lee, M.-J. Edward, Hiok-Tiaq Ng |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Sep2004, Vol. 39 Issue 9, p1553-1561, 9p, 17 Color Photographs, 8 Diagrams, 1 Graph |
| Abstrakt: |
A 0.622-8.Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-µm CMOS CDR consumes 33 mW at 8 Gb/s. Die area including voltage regulator is 0.08 mm². Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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