| Abstrakt: |
With the advent of embedded vision systems, smart sensors with integrated image signal processing (ISP) become a hot topic. This poses a need for efficient hardware implementation, regarding resource utilization and power consumption, of core image processing algorithms. Power consumption is especially important, since many of the target devices are usually battery operated. Edge-aware filtering, although it is used in many core image processing algorithms, is still challenging operation, especially in cases where large kernels are needed. In this paper, efficient hardware realization of fast guided filter (FGF) is proposed. It is based on idea that large filter of size R = K · S can be calculated by downsampling input image by factor S and using filter of size K. Besides reduced memory and logic requirements, this optimization enables that, for the scaling factor S, core processing is done at 1 / S 2 pixel clock, providing significantly lower power consumption. Experimental results on Cyclone V FPGA chip demonstrate that, for FGF of size 35 × 35 with downsampling factor S = 7 , the proposed design achieves 60 fps for 1080p video. Memory utilization is 147.3 kB without need for any off-chip memory. Core dynamic power consumption is 79.89 mW. Proposed design consumes less total power than state-of-the-art guided filter realizations including ASIC-based solutions. This module can be seamlessly integrated into smart sensors ISP units, because it is designed for power-efficient streaming processing. [ABSTRACT FROM AUTHOR] |
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