| Autor: |
Yamada, Yutaka, Uchiyama, Masato, Jobashi, Masashi, Koizumi, Tomohiro, Tamai, Takanori, Sato, Nobuhiro, Tanabe, Jun, Kimura, Katsuyuki, Ojima, Yoshinari, Murakami, Ryusuke, Yoshikawa, Takashi, Sano, Toru, Tanabe, Yasuki, Ishigaki, Yutaro, Hosoda, Soichiro, Hyuga, Fumihiko, Moriya, Akira, Hada, Ryuji, Masuda, Atsushi |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jan2020, Vol. 55 Issue 1, p120-132, 13p |
| Abstrakt: |
Advanced driver-assistance systems (ADASs) that provide machine support to avoid critical accidents are already in wide use in vehicles in today’s market. SoCs for such systems have several requirements: 1) high computational performance to run several advanced algorithms at low latency; 2) low power consumption to permit running under the extreme heat and power conditions of real-world vehicles; and 3) high reliability to reduce the risk of serious accidents caused by faults. This article presents a novel SoC for ADAS applications, which resolves these difficult challenges. To achieve high performance with low power consumption, the SoC adopts the heterogeneous architecture, with ten processors, four DSPs, and eight types of accelerators, including the DNN accelerator and the image signal processor (ISP). To achieve higher reliability, the SoC implements several safety mechanisms, including system partitioning to prevent fault propagation, diagnostic features to detect faults, and a dedicated controller to operate runtime built-in self-test (BIST) of the ISP’s diagnostic features during the vertical blanking interval (VBLANK). The SoC is implemented in a 16-nm process, and its size is 94.52 mm2. Peak performance of 20.5 TOPS and low power consumption of 9.78 W are achieved. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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