| Autor: |
Shirahama, Hiroyuki, Taniguchi, Kenji, Nakashi, Kenichi |
| Předmět: |
|
| Zdroj: |
Electronics & Communications in Japan, Part 2: Electronics; Dec95, Vol. 78 Issue 12, p104-114, 11p |
| Abstrakt: |
With the development of high-speed digital communications, e.g., optical fiber communications, smaller, faster, retiming devices are being required. The phase-locked loops (PLLs) are suited to an integration compared to surface acoustic wave (SAW) or liquid crystal (LC) passive filters. Therefore, PLLs have been put to use gradually as clock extraction devices many frequency range over 100 MHz. The authors have developed the previously reported PLL with frequency difference detector (FDD) to provide a new function, which is useful to overcome the pseudo-lock problem in conventional retiming PLLc and also improved performance of the FDD. The proposed PLL has been constructed with ECL-IC, PLA and other discrete parts. It has been evaluated experimentally and the PLL designed with a 0.8-μ design-rule bipolar transistor has been evaluated by simulation to confirm the following characteristics. 1. The PLL can detect an initial unlock state and pseudo-lock state within almost the same time as FDD sampling time and can recover rapidly. 2. The jitter transfer function is almost equal to the usual first-order PLL and is independent of input data patterns. 3. The FDD frequency detecting range, corresponding to the PLL lock-in range, is more than four times that of the previously proposed FDD-PLL. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
