| Autor: |
Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jul2004, Vol. 39 Issue 7, p1101-1109, 9p, 9 Black and White Photographs, 9 Diagrams, 1 Chart, 5 Graphs |
| Abstrakt: |
A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-µm pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm² and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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