| Autor: |
Bhardwaj, Swati, Raghuraman, Shashank, Acharyya, Amit |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; May2019, Vol. 27 Issue 5, p1124-1137, 14p |
| Abstrakt: |
This paper proposes an $n$ -dimensional Simplex FastICA (FICA), an accelerated and low complex architectural design methodology for FICA to attain high computation speed targeted for resource-constrained applications. This is achieved by exploiting the algorithmic redundancies of FICA that make the proposed Simplex FICA faster than the conventional FICA without adding any extra architectural complexities. The proposed methodology has been verified and validated by applying it for separating 6D EEG signals. Subsequently, the corresponding hardware has been designed using Verilog HDL. It is synthesized using UMC 90-nm technology resulting in 0.5703-mW power and 0.495 mm2 area at 1.08 V. The computation time saving for 4D–12D FICA was computed by varying the number of iterations of convergence for the $n\text {th}$ stage from 2 to 4 for 4096 samples. The average percentage of computation time saved for $n\text {th}$ stage achieved with the proposed methodology in comparison to the state of the art varies from 99.783% to 99.891%. The overall average percentage of computation time saving for the proposed design with the aforementioned specifications varies from 9.14% to 16.6%. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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