| Autor: |
Meinerzhagen, Pascal A., Tokunaga, Carlos, Malavasi, Andres, Vaidya, Vaibhav, Mendon, Ashwin, Mathaikutty, D., Kulkarni, Jaydeep, Augustine, Charles, Cho, Minki, Kim, Stephen T., Matthew, George E., Jain, Rinkle, Ryan, Joseph, Peng, Chung-Ching, Paul, Somnath, Vangal, Sriram, Perez Esparza, Brando, Cuellar, L., Woodman, M., Iyer, Bala |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jan2019, Vol. 54 Issue 1, p144-157, 14p |
| Abstrakt: |
Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and $V_{\text {MIN}}$ optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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