| Autor: |
Toriyama, Yuta, Markovic, Dejan |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Aug2018, Vol. 53 Issue 8, p2378-2388, 11p |
| Abstrakt: |
Non-binary low-density parity-check (NB-LDPC) codes are a promising class of error-correcting codes that provide excellent coding gain beyond that of their binary counterparts. However, their decoding complexity has thus far limited practicality. We present an NB-LDPC decoder with information throughput of 2.267 Gb/s and power consumption of 212.4 mW, yielding an energy efficiency of 93.7 pJ/bit, implemented in 40-nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor and making the code appropriate for storage applications. A logarithmic quantization scheme is proposed to enable aggressive wordlength reduction to alleviate hardware complexity. In addition, a dual-decoding algorithm scheme is employed to alleviate the computational complexity of decoding, realized in an efficient architecture with high parallelism and avoidance of idle clock cycles. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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