| Autor: |
DeBrosse, John, Gogl, Dietmar, Bette, Alexander, Hoenigschmid, Heinz, Robertazzi, Raphael, Arndt, Christian, Braun, Daniel, Casarotto, D., Havreluk, R., Lammers, Stefan, Obermaier, Werner, Reohr, William R., Viehmann, H., Gallagher, William J., Müller, Gerhard |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Apr2004, Vol. 39 Issue 4, p678-683, 6p |
| Abstrakt: |
A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-μm VDD = 1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-μm² one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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