| Autor: |
Koon-Lun Jackie Wong, Behzad, Hatamkhani, Hamid, Mansuri, Mozhgan, Chih-Kong Ken Yang |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Apr2004, Vol. 39 Issue 4, p602-612, 11p |
| Abstrakt: |
This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm² in a 0.18-μm 1.8-V CMOS technology. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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