| Autor: |
Akter, Md Shakil, Makinwa, Kofi A. A., Bult, Klaas |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Apr2018, Vol. 53 Issue 4, p1115-1126, 12p |
| Abstrakt: |
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 \times gain, it achieves −100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 \mu \text{W} at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 \times$ compared with that of state-of-the-art high-linearity amplifiers. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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