| Autor: |
Yeh, Shang-Fu, Chou, Kuo-Yu, Tu, Hon-Yih, Chao, Calvin Yi-Ping, Hsueh, Fu-Lung |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Feb2018, Vol. 53 Issue 2, p527-537, 11p |
| Abstrakt: |
This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1- \mu \textm pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm2. This paper achieves a 0.66erms− with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/−0.94 LSB to +0.29 LSB/−0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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