Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops.
| Autor: | Ali, Fara Ashikin Binti, Hashizume, Masaki, Ikiri, Yuki, Yotsuyanagi, Hiroyuki, Lu, Shyue-Kung |
|---|---|
| Zdroj: | 2016 IEEE CPMT Symposium Japan (ICSJ); 2016, p137-138, 2p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|