| Autor: |
Byung-Moo Min, Kim, Peter, Bowman III, Frederick W., Boisvert, David M., Aude, Arlo J. |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Dec2003, Vol. 38 Issue 12, p2031-2039, 9p, 5 Black and White Photographs, 9 Diagrams, 1 Chart, 7 Graphs |
| Abstrakt: |
A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-µm dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm². [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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