Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip.
| Autor: | Koike, Hiroki, Miura, Sadahiko, Honjo, Hiroaki, Watanabe, Toshinari, Sato, Hideo, Sato, Soshi, Nasuno, Takashi, Noguchi, Yasuo, Yasuhira, Mitsuo, Tanigawa, Takaho, Muraguchi, Masakazu, Niwa, Masaaki, Ito, Kenchi, Ikeda, Shoji, Ohno, Hideo, Endoh, Tetsuo |
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| Zdroj: | 2016 IEEE 8th International Memory Workshop (IMW); 2016, p1-4, 4p |
| Databáze: | Complementary Index |
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