Power model analysis using variable rate clock network in CMOS processor.
| Autor: | Titus, T. Joby, Vijayakumari, V., Saranya, B., Devi, V.S. Sanjana |
|---|---|
| Zdroj: | ACM International Conference Proceeding Series; 7/6/2016, p1-5, 5p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|