Autor: |
Baranov, G., Milenin, A., Baklanov, M. |
Předmět: |
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Zdroj: |
Russian Microelectronics; May2016, Vol. 45 Issue 3, p186-190, 5p |
Abstrakt: |
The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the 'fin' structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
Externí odkaz: |
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