Test method and scheme for low-power validation in modern SOC integrated circuits.
| Autor: | Bhaskaran, Bonita, Sanghani, Amit, Narayanun, Kaushik, Abdollahian, Ayub, Laknaur, Amit |
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| Zdroj: | 2016 IEEE 34th VLSI Test Symposium (VTS); 2016, p1-6, 6p |
| Databáze: | Complementary Index |
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