| Autor: |
Taito, Yasuhiko, Tanizaki, Tetsushi, Kinoshita, Mitsuya, Igaue, Futoshi, Fujino, Takeshi, Arimoto, Kazutami |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Nov2003, Vol. 38 Issue 11, p1967-1973, 7p, 7 Black and White Photographs, 11 Diagrams, 2 Charts, 1 Graph |
| Abstrakt: |
This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-µm logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 µW owing to the hierarchical power supply and SSR. The macro size is 4.59 mm². The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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