| Autor: |
Jong-Seok Moon, Takayasu, Athas, William C., Soli, Sigfrid D., Draper, Jeffrey T., Beerel, Peter A. |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2003, Vol. 11 Issue 5, p762-777, 16p, 12 Diagrams, 2 Charts, 14 Graphs |
| Abstrakt: |
We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC[sub L]V² at 15 MHz and 97.8 pF load. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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