FPGA implementation of an optimized 8-bit AES architecture: A masked S-Box and pipelined approach.
| Autor: | Chawla, Simarpreet Singh, Aggarwal, Swapnil, Kamal, Snigdha, Goel, Nidhi |
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| Zdroj: | 2015 IEEE International Conference on Electronics, Computing & Communication Technologies (CONECCT); 2015, p1-6, 6p |
| Databáze: | Complementary Index |
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