Dynamic current reduction of CMOS digital circuits through design and process optimization.
| Autor: | Innocenti, J., Welter, L., Borrel, N., Julien, F., Portal, J.M., Sonzogni, J., Lopez, L., Masson, P., Niel, S., Dreux, P., Castellan, J. |
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| Zdroj: | 2015 25th International Workshop on Power & Timing Modeling, Optimization & Simulation (PATMOS); 2015, p77-81, 5p |
| Databáze: | Complementary Index |
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